Improving mixed-signal SOC testing: a power-aware reuse-based approach with analog BIST
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
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The simultaneous operation of multiple embedded analog test cores is investigated throughexperiments on a prototype integrated circuit containing eight such cores. Each core consists of a scan memory, some passive filters, and a fully synchronized integrated waveform digitizer for signal extraction. The circuit supports fully differential signal generation and digitization and employs common circuit techniques to enhance robustness to process variation. Simultaneousoperation is demonstrated to achieve over 12-bits of amplitude resolution and more than 70 dB SFDR over a 20 MHz bandwidth. Matching issues are investigated, and instrument uniformity across about 250 cores is verified by measuring waveform generator offset errors, digitizer offset errors, and test core frequency response variability.