Modeling and performance evaluation of ATM switches
AIC'05 Proceedings of the 5th WSEAS International Conference on Applied Informatics and Communications
Input register architectures of high speed router for supporting the PHB of differentiated services
QoS-IP'05 Proceedings of the Third international conference on Quality of Service in Multiservice IP Networks
A genetic algorithm of high-throughput and low-jitter scheduling for input-queued switches
ICNC'05 Proceedings of the First international conference on Advances in Natural Computation - Volume Part III
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The input-queued switching architecture is becoming the alternative architecture for high speed switches owing to its scalability. Tremendous amount of effort has been made to overcome the throughput problem caused by head of line blocking and the contentions occurred at input and output sides of a switch. Existing algorithms only aim at improving throughput but inadvertently ignore undesired effects on the traffic shape and quality of service features such as delay and fairness. In this paper, a new algorithm, referred to as longest normalized queue first, is introduced to improve upon existing algorithms in terms of delay, fairness and burstiness. The proposed algorithm is proven to be stable for all admissible traffic patterns. Simulation results confirm that the algorithm can smooth the traffic shape, and provide good delay property as well as fair service.