Intelligent RAM (IRAM): the Industrial Setting, Applications, and Architectures

Authors:
Affiliations:
Venue:
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
Year:
1997

Citing 0
Cited 7

Active disks: programming model, algorithms and evaluation

Proceedings of the eighth international conference on Architectural support for programming languages and operating systems
Exploring multimedia applications locality to improve cache performance

MULTIMEDIA '00 Proceedings of the eighth ACM international conference on Multimedia
An Efficient Data Location Protocol for Self.organizing Storage Clusters

Proceedings of the 2003 ACM/IEEE conference on Supercomputing
Memory In Processor-Supercomputer On a Chip: Processor Design and Execution Semantics for Massive Single-Chip Performance

IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 14 - Volume 15
FPGA-Array with Bandwidth-Reduction Mechanism for Scalable and Power-Efficient Numerical Simulations Based on Finite Difference Methods

ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Prototype implementation of array-processor extensible over multiple FPGAs for scalable stencil computation

ACM SIGARCH Computer Architecture News
Portable, flexible, and scalable soft vector processors

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Quantified Score

Hi-index	0.00

Visualization

Abstract

The goal of Intelligent RAM (IRAM) is to design a cost-effective computer by designing a processor in a memory fabrication process, instead of in a conventional logic fabrication process, and include memory on-chip. To design a processor in a DRAM process one must learn about the business and culture of the DRAMs, which is quite different from microprocessors. We describe some of those differences, and then our current vision of IRAM applications, architectures, and implementations.