Functional Implementation Techniques for CPU Cache Memories
IEEE Transactions on Computers - Special issue on cache memory and related problems
Chip integration methodology for the IBM S/390 G5 and G6 custom microprocessors
IBM Journal of Research and Development
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The S/390 G4 CMOS processor is an implementation of the IBM ESA/390 architecture on a single custom CMOS chip. It is a new design which uses a straightforward pipeline both to achieve a fast cycle time and to speed the design cycle. The complex instructions are implemented using a highly privileged subroutines called millicode. To achieve high data integrity while maintaining a high clock frequency, the chip contains duplicate I- and E-units which perform the same operations each cycle and have their results compared.