Designing a Modern Memory Hierarchy with Hardware Prefetching
IEEE Transactions on Computers
Compiler-Directed Cache Assist Adaptivity
ISHPC '00 Proceedings of the Third International Symposium on High Performance Computing
Compiler-Directed Cache Line Size Adaptivity
IMS '00 Revised Papers from the Second International Workshop on Intelligent Memory Systems
Static analysis of parameterized loop nests for energy efficient use of data caches
Compilers and operating systems for low power
Dynamic techniques to reduce memory traffic in embedded systems
Proceedings of the 1st conference on Computing frontiers
Line Size Adaptivity Analysis of Parameterized Loop Nests for Direct Mapped Data Cache
IEEE Transactions on Computers
Proceedings of the 33rd annual international symposium on Computer Architecture
Victim management in a cache hierarchy
IBM Journal of Research and Development - Advanced silicon technology
Revisiting Cache Block Superloading
HiPEAC '09 Proceedings of the 4th International Conference on High Performance Embedded Architectures and Compilers
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In this paper we examine the application of offline algorithms for determining the optimal sequence of loads and superloads (a load of multiple consecutive cache lines) for direct-mapped caches. We evaluate potential gains in terms of miss rate and bandwidth and find that in many cases optimal superloading can noticeably reduce the miss rate without appreciably increasing bandwidth. Then we examine how this performance potential might be realized. We examine the effectiveness of a dynamic online algorithm and of static analysis (profiling) for superloading and compare these to next-line prefetching. Experimental results show improvements comparable to those of the optimal algorithm in terms of miss rates.