Multilevel reverse most-significant carry computation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
Multilevel Reverse-Carry Addition: Single and Dual Adders
Journal of VLSI Signal Processing Systems
Multilevel Reverse-Carry Adder
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Area-Time Efficient Sign Detection Technique for Binary Signed-Digit Number System
IEEE Transactions on Computers
Revisiting integer multiplication overflow
SEPADS'05 Proceedings of the 4th WSEAS International Conference on Software Engineering, Parallel & Distributed Systems
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A fast calculation of the most-significant carry in an addition is required in several applications, such as comparisons of two operands by performing their difference, sign detection, and overflow detection. It has been proposed to calculate this carry by detecting the most-significant carry chain and collecting the carry after this chain. The detection can be implemented by a prefix tree of AND gates and the collecting by a multi-input OR or by a connection with tri-state buffers.We have performed an estimate of the delay of this implementation for a data-path width of 64 bits and conclude that it is not significantly faster than the traditional carry-look-ahead based method.We propose a multilevel implementation, which allows the overlap of successive levels thereby reducing the overall delay. For 64-bit operands we estimate a delay reduction of about 15% with respect to the traditional carry-look-ahead based method, with a similar number of gates and number and length of interconnections.