Dynamic Loop Caching Meets Preloaded Loop Caching " A Hybrid Approach

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Venue:
ICCD '02 Proceedings of the 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD'02)
Year:
2002

Citing 0
Cited 4

Clustered Loop Buffer Organization for Low Energy VLIW Embedded Processors

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Lightweight runtime control flow analysis for adaptive loop caching

Proceedings of the 20th symposium on Great lakes symposium on VLSI
Low power engineering

Embedded Systems Design
Combining code reordering and cache configuration

ACM Transactions on Embedded Computing Systems (TECS)

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Abstract

Dynamically-loaded tagless loop caching reduces instruction fetch power for embedded software with small loops, but only supports simple loops without taken branches. Preloaded tagless loop caching supports complex loops with branches and thus can reduce power further, but has a limit on the total number of instructions cached. We show that each does well on particular benchmarks, but neither is best across all of those benchmarks. We present a new hybrid loop cache that only preloads the complex loops, while dynamically loading other loops, thus achieving the strengths of each approach. We demonstrate better power savings than either previous approach alone.