ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
Formalized methodology for data reuse exploration in hierarchical memory mappings
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
The filter cache: an energy efficient memory structure
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
Pipeline gating: speculation control for energy reduction
Proceedings of the 25th annual international symposium on Computer architecture
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Data speculation support for a chip multiprocessor
Proceedings of the eighth international conference on Architectural support for programming languages and operating systems
Using dynamic cache management techniques to reduce energy in a high-performance processor
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Compiling for Speculative Architectures
LCPC '99 Proceedings of the 12th International Workshop on Languages and Compilers for Parallel Computing
The Potential for Using Thread-Level Data Speculation to Facilitate Automatic Parallelization
HPCA '98 Proceedings of the 4th International Symposium on High-Performance Computer Architecture
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We present a new software scheme, called compiler-assisted I-cache prediction (CIP) for energy reduction in instruction caches. With the help of compiler-supplied information, the processor is able to turn off substantial portions of the I-cache. The necessary cache sets are only turned on during the execution of individual code sections. The CIP scheme is based on the processor's ability to predict code sections that are about to execute and on the compiler's ability to precisely inform the hardware about the size of these code sections. Our techniques grew out of work with optimizing compilers for speculative parallel microarchitectures. The use of this target machine class is further motivated by the fact that speculative processors have the potential to overcome limitations in the compiler parallelization of many applications, especially non-numerical programs. Speculative microarchitectures are also among the most promising emerging architectures that can take advantage of the ever-increasing levels of chip integration. We will show that our new techniques can lead up to 90% I-cache energy savings in general-purpose applications without significant execution overhead. We believe that this is a substantial step towards the goal of making such chips integral parts of mobile computing devices, such as laptops, palm tops, and cellular phones.