A shift-register-based QCA memory architecture
ACM Journal on Emerging Technologies in Computing Systems (JETC)
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The need for small, high speed, low power computers asthe end of Moore's law approaches s driving research intonanotechnology. These novel devices have significantly different properties than traditional MOS devices and requirenew design methodologies, which in turn provide excitingarchitectural opportunities. The H-memory is a design developed for a particular nanotechnology, quantum-dot cellular automata. We propose a new execution model thatmerges with the H-memory to exploit the characteristics ofthis nanotechnology by distributing the functionality of theCPU throughout the memory structure.