Low-power, low-complexity instruction issue using compiler assistance
Proceedings of the 19th annual international conference on Supercomputing
Reconfigurable hardware for high-security/high-performance embedded systems: the SAFES perspective
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Combining Edge Vector and Event Counter for Time-Dependent Power Behavior Characterization
Transactions on High-Performance Embedded Architectures and Compilers II
Efficient program power behavior characterization
HiPEAC'07 Proceedings of the 2nd international conference on High performance embedded architectures and compilers
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By anticipating when resources will be idle, it is possibleto reconfigure the hardware to reduce power consumptionwithout significantly reducing performance. This requirespredicting what the resource requirements will be for anapplication. In the past, researchers have taken one of twoapproaches: design hardware monitors that can measurerecent performance, or profile the application to determinethe most likely behavior for each block of code. This paperexplores a third option which is to combine hardwaremonitoring with software profiling to achieve lower powerutilization than either method alone. We demonstrate thepotential for this approach in two ways. First, we comparehardware monitoring and software profiling of IPC for codeblocks and show that they capture different information. Bycombining them, we can control issue width and ALU usagemore effectively to save more power. Second, we showthat anticipating stalls due to critical load misses in the L2cache can enable fetch halting. Again, hardware monitoringand software profiling must be used together to effectivelypredict misses and criticality of loads.