Design and validation with HDL Verilog of a complex input/output processor for an ATM switch: the CMC

• Authors: J. C. Diaz;P. Plaza;L. A. Merayo;P. Scarfone;M. Zamboni
• Venue: IVC '95 Proceedings of the 4th IEEE International Verilog HDL Conference
• Year: 1995

This paper describes the design and validation of a complex ASIC through the use of Verilog HDL. The CMC is an interface circuit for ATM cells, part of a 2.5 Gb/s switching fabric. Its main function is serial to parallel and parallel to serial data conversion; another features like VPINCI translation, cell counting, insertion and extraction from an external microprocessor are also included. The validation and verification of the circuit implementation was carried out by simulating the different level of abstractions of the circuit descriptions thoroughly with Verilog-XL. An ECL cell Verilog library was written to be able to perform simulations of the complete circuit. The CMC is a 0.7 um BiCMOS IC, containing ECL and CMOS blocks, The complexity of the circuit is 320 Ktransistors on a die size of 224 mm/sup 2/. It has been encapsulated on a 319 pins CPGA package, dissipating 8.2 Watts at full speed.