Embedded Systems Design
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Advances in semiconductor technology have several impacts on processor design. One impact is that faster clock rates and slower wires will limit the number of transistors reachable in a single cycle. Another impact is that power management is becoming a design constraintdue to increase in power density. A small LO cache on top of a traditional Ll cache has the advantages of shorter access time and lower power consumption. The downside of a LO cache is possible performance loss in case of cache misses. In this paper, we have analyzed LO instruction cache miss patterns and have proposed an effective LO instruction cache management scheme through history-based prediction. For SPEC2OOO benchmarks, the prediction hit rate is as high as 99% and the average hit rate is more than 93%. Compared to other LO instruction cache management schemes, our scheme reduces more than 95% of theperformance degradation in LO caches while maintaining the energy advantage as shown by a lower energy-delay product.