Permission accounting in separation logic
Proceedings of the 32nd ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Proceedings of the 2005 ACM SIGPLAN conference on Programming language design and implementation
SpliceNP: a TCP splicer using a network processor
Proceedings of the 2005 ACM symposium on Architecture for networking and communications systems
Accelerating database operators using a network processor
DaMoN '05 Proceedings of the 1st international workshop on Data management on new hardware
High-throughput sketch update on a low-power stream processor
Proceedings of the 2006 ACM/IEEE symposium on Architecture for networking and communications systems
Resource allocation in network processors for network intrusion prevention systems
Journal of Systems and Software
An ILP formulation for system-level application mapping on network processor architectures
Proceedings of the conference on Design, automation and test in Europe
ILP and heuristic techniques for system-level design on network processor architectures
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A generic component model for building systems software
ACM Transactions on Computer Systems (TOCS)
A throughput-driven task creation and mapping for network processors
HiPEAC'07 Proceedings of the 2nd international conference on High performance embedded architectures and compilers
Compilation of stream programs for multicore processors that incorporate scratchpad memories
Proceedings of the Conference on Design, Automation and Test in Europe
Evaluating regular expression matching engines on network and general purpose processors
Proceedings of the 5th ACM/IEEE Symposium on Architectures for Networking and Communications Systems
Enhancing counting bloom filters through Huffman-coded multilayer structures
IEEE/ACM Transactions on Networking (TON)
Differential encoding of DFAs for fast regular expression matching
IEEE/ACM Transactions on Networking (TON)
A register allocation framework for banked register files with access constraints
ACSAC'05 Proceedings of the 10th Asia-Pacific conference on Advances in Computer Systems Architecture
Hint-based cache design for reducing miss penalty in HBS packet classification algorithm
Journal of Parallel and Distributed Computing
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From the Publisher:Software and firmware engineers developing products based on the Intel IXP2400 or IXP2800 network processors will find this guide to be an invaluable resource, whether they are new to programming Intel network processors or already familiar with the IXP1200 processor. Users will progress through a set of tasks typically faced by network software engineers, from basic receive and transmit operations to more complex packet processing. Each task is deconstructed, through working example code, into what the appropriate parts of the software and hardware can do and why it is important to the design and implementation. The various tradeoffs that are possible within the software and hardware are also fully analyzed. This coding guide progresses in steps from simple, single-threaded programs to a complete multithreaded reference application using the microblock programming paradigm. Application and programming notes are used throughout to accelerate the pace for readers already familiar with IXP1200 programming. Complete and working code examples from the book and the Intel IXA Software Developer's Kit are included on the CD-ROM.Author Biography: Eric J. Johnson and Aaron R. Kunze are senior network software engineers with Intel's research and development group. They designed and implemented the microACE architecture in the IXP12xx Software Development Kit, which helps software engineers create reusable packet-processing modules and combine them into network processor applications. They also designed reusable Quality of Service (QoS) components for use with Intel's network processor family. They are the coauthors of IXP1200 Programming. They live in Portland, Oregon.