The priority-based coloring approach to register allocation
ACM Transactions on Programming Languages and Systems (TOPLAS)
POPL '96 Proceedings of the 23rd ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Journal of the ACM (JACM)
Multiple-banked register file architectures
Proceedings of the 27th annual international symposium on Computer architecture
Register Allocation for Banked Register File
OM '01 Proceedings of the 2001 ACM SIGPLAN workshop on Optimization of middleware and distributed systems
Proceedings of the joint conference on Languages, compilers and tools for embedded systems: software and compilers for embedded systems
Reducing the complexity of the register file in dynamic superscalar processors
Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture
Taming the IXP network processor
PLDI '03 Proceedings of the ACM SIGPLAN 2003 conference on Programming language design and implementation
PACT '00 Proceedings of the 2000 International Conference on Parallel Architectures and Compilation Techniques
Banked multiported register files for high-frequency superscalar microprocessors
Proceedings of the 30th annual international symposium on Computer architecture
Ixp2400-2800 Programming: The Complete Microengine Coding Guide
Ixp2400-2800 Programming: The Complete Microengine Coding Guide
Resolving Register Bank Conflicts for a Network Processor
Proceedings of the 12th International Conference on Parallel Architectures and Compilation Techniques
Proceedings of the 2005 ACM SIGPLAN conference on Programming language design and implementation
Mobile Information Systems - Mobile and Wireless Networks
ACM Transactions on Embedded Computing Systems (TECS)
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Banked register file has been proposed to reduce die area, power consumption, and access time. Some embedded processors, e.g. Intel’s IXP network processors, adopt this organization. However, they expose some access constraints in ISA, which complicates the design of register allocation. In this paper, we present a register allocation framework for banked register files with access constraints for the IXP network processors. Our approach relies on the estimation of the costs and benefits of assigning a virtual register to a specific bank, as well as that of splitting it into multiple banks via copy instructions. We make the decision of bank assignment or live range splitting based on analysis of these costs and benefits. Compared to previous works, our framework can better balance the register pressure among multiple banks and improve the performance of typical network applications.