Upper bounds to processor-time tradeoffs under bounded-speed message propagation
Proceedings of the seventh annual ACM symposium on Parallel algorithms and architectures
On the Space and Access Complexity of Computation DAGs
WG '00 Proceedings of the 26th International Workshop on Graph-Theoretic Concepts in Computer Science
Graph expansion and communication costs of fast matrix multiplication: regular submission
Proceedings of the twenty-third annual ACM symposium on Parallelism in algorithms and architectures
Graph expansion and communication costs of fast matrix multiplication
Journal of the ACM (JACM)
Graph expansion analysis for communication costs of fast rectangular matrix multiplication
MedAlg'12 Proceedings of the First Mediterranean conference on Design and Analysis of Algorithms
Processor--Time Tradeoffs under Bounded-Speed Message Propagation: Part I, Upper Bounds
Theory of Computing Systems
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The speed of CPUs is accelerating rapidly, outstripping that of peripheral storage devices and making it increasingly difficult to keep CPUs busy. Multilevel memory hierarchies, scaled to simulate single-level memories, are increasing in importance. In this paper we introduce the Memory Hierarchy Game, a multilevel pebble game simulating data movement in memory hierarchies. We derive upper and lower bounds on the I/O and computation time for a number of problems, including matrix multiplication and the Fourier transform, and discuss conditions on hierarchies under which they act as fast memories.