Type architectures, shared memory, and the corollary of modest potential
Annual review of computer science vol. 1, 1986
A model for hierarchical memory
STOC '87 Proceedings of the nineteenth annual ACM symposium on Theory of computing
An introduction to parallel algorithms
An introduction to parallel algorithms
Horizons of parallel computation
Journal of Parallel and Distributed Computing
The Parallel Evaluation of General Arithmetic Expressions
Journal of the ACM (JACM)
Lower Bounds to Processor-Time Tradeoffs under Bounded-Speed Message Propagation
WADS '95 Proceedings of the 4th International Workshop on Algorithms and Data Structures
Space-Time Tradeoffs in Memory Hierarchies
Space-Time Tradeoffs in Memory Hierarchies
Time bounded random access machines
Journal of Computer and System Sciences
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Upper bounds are derived for the processor--time tradeoffs of machines such as linear arrays and two-dimensional meshes, which are compatible with the physical limitation expressed by bounded-speed propagation of messages (due to the finiteness of the speed of light). It is shown that parallelism and locality combined may yield speedups superlinear in the number of processors. The speedups are inherent, due to the optimality of the obtained tradeoffs as established in a companion paper.Simulations of multiprocessor machines are developed by analogous machines with fewer processors. A crucial role is played by the hierarchical nature of the memory system. A divide-and-conquer technique for hierarchical memories is developed, based on the graph-theoretic notion of a topological separator. For multiprocessors, this technique also requires a careful balance of memory access and interprocessor communication costs, which leads to nonintuitive orchestrations of the simulation process.