Automatic tub region generation for symbolic layout compaction

Authors:
C.-Y. Lo
Affiliations:
AT&T Bell Laboratories, 600 Mountain Avenue, Murray Hill, NJ
Venue:
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Year:
1989

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Abstract

This paper describes a new algorithm that automatically generates tub regions for VLSI symbolic layouts with quality comparable to that of human designers. The algorithm supports an explicit modeling of enclosure rules in the layout compaction task with the benefit of robustness and reduced output database size. In addition, the algorithm runs at O(n2) time and O(n) space with the expected run time of O(nlogn).