A Novel Discrete Relaxation Architecture
IEEE Transactions on Pattern Analysis and Machine Intelligence
| Hi-index | 4.10 |
The authors review the research done on a structured, symbol-based IC design method called path programmable logic (PPL). They explain the logic partitioning strategy on which PPL is based. Compared to full-custom design methods, the PPL methods permits an order of magnitude reduction in design time. In most cases, the density of the circuits designed using the PPL method approaches or surpasses that of the practical full-custom designs. Compared to semicustom design techniques such as standard cells and gate arrays, PPL reduces the design time by a factor of three while improving the densities by a factor of two to three.