Parallel Computer Architectures and Problem Solving Strategies for the Consistent Labeling Problem
IEEE Transactions on Computers
A Parallel Architecture for Discrete Relaxation Algorithm
IEEE Transactions on Pattern Analysis and Machine Intelligence
Parallel split-level relaxation
Parallel split-level relaxation
The future of high performance computers in science and engineering
Communications of the ACM - Special issue: multiprocessing
IEEE Spectrum
Generating Semantic Descriptions From Drawings of Scenes With Shadows
Generating Semantic Descriptions From Drawings of Scenes With Shadows
SIMON: a Simulator of Multicomputer Networks
SIMON: a Simulator of Multicomputer Networks
A Mathematical Theory of Communication
A Mathematical Theory of Communication
A modular partitioning approach for asynchronous circuit synthesis
DAC '94 Proceedings of the 31st annual Design Automation Conference
A divide-and-conquer approach for asynchronous interface synthesis
ISSS '94 Proceedings of the 7th international symposium on High-level synthesis
Trace-Based Methods for Solving Nonlinear Global Optimization and Satisfiability Problems
Journal of Global Optimization
A Discrete Lagrangian-Based Global-SearchMethod for Solving Satisfiability Problems
Journal of Global Optimization
Convergence Properties of Optimization Algorithms for the SAT Problem
IEEE Transactions on Computers
Global Optimization for Satisfiability (SAT) Problem
IEEE Transactions on Knowledge and Data Engineering
A new, cellular automaton-based, nearest neighbor pattern classifier and its VLSI implementation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 0.16 |
The discrete relaxation algorithm (DRA) is a computational technique that enforces arc consistency (AC) in a constraint satisfaction problem (CSP). The original sequential AC-1 algorithm suffers from O(n/sup 3/m/sup 3/) time complexity, and even the optimal sequential AC-4 algorithm is O(n/sup 2/m/sup 2/) for an n-object and m-label DRA problem. Sample problem runs show that these algorithms are all too slow to meet the need for any useful, real-time CSP applications. A parallel DRA5 algorithm that reaches a lower bound of O(nm) (where the number of processors is polynomial in the problem size) is given. A fine-grained, massively parallel hardware computer architecture has been designed for the DRA5 algorithm. For practical problems, many orders of magnitude of efficiency improvement can be reached on such a hardware architecture.