Hard-Fault Detection and Diagnosis During the Application of Model-Based Data Converter Testing
Journal of Electronic Testing: Theory and Applications
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For next generation deep sub-micron (DSM) analogue and mixed signal ICs, the integration of Design-for-Test (DfT), Design-for-Manufacturability (DfM), Defect-Oriented Test (DOT) approaches, and Built-In Self-Test (BIST) techniques into the design and manufacturing cyclewill gain increasing importance in the context of implementing a structural IC test methodology [1].This paper discusses the relevance of fault simulation techniques to investigate realistic circuit failure modes and test requirements. It is shown for an ADC target design that hard faults frequently cause marginal rather than catastrophic failure, hence have to be subject to test.