Test Resource Partitioning and Reduced Pin-Count Testing Based on Test Data Compression

Authors:
A. Chandra;K. Chakrabarty
Affiliations:
Department of Electrical and Computer Engineering, Duke University, Durham, NC;Department of Electrical and Computer Engineering, Duke University, Durham, NC
Venue:
Proceedings of the conference on Design, automation and test in Europe
Year:
2002

Citing 0
Cited 4

On test data compression and n-detection test sets

Proceedings of the 40th annual Design Automation Conference
Test Data Compression and Test Resource Partitioning for System-on-a-Chip Using Frequency-Directed Run-Length (FDR) Codes

IEEE Transactions on Computers
Synchronization overhead in SOC compressed test

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Test data compression scheme based on variable-to-fixed-plus-variable-length coding

Journal of Systems Architecture: the EUROMICRO Journal

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Abstract

We present a new test resource partitioning (TRP) techniquefor reduced pin-count testing of system-on-a-chip(SOC). The proposed technique is based on test datacompression and on-chip decompression. It makes effectiveuse of frequency-directed run-length codes, internalscan chains, and boundary scan chains. The compression/decompression scheme decreases test data volume andthe amount of data that has to be transported from the testerto the SOC. We show via analysis as well as through experimentsthat the proposed TRP scheme reduces testing timeand allows the use of a slower tester with fewer I/O channels.Finally, we show that an uncompacted test set appliedto an embedded core after on-chip decompression is likelyto increase defect coverage.