Integration of Reconfigurable Hardware into System-Level Design
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
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In this paper, we present an efficient methodology tovalidate high performance algorithms and prototype themusing reconfigurable hardware. We follow a strict top-downHardware/Software Codesign paradigm using step-wiserefinement techniques. Starting from a performanceevaluation on the data-flow level using the OCAPI system,we partition the simulated high-level data-flow descriptioninto hardware and software modules. The hardware parts,described in Handel-C, are compiled and mapped to XilinxVirtex 2000E FPGAs, and the software is executed on a PCprocessor that hosts the Virtex boards. Hardware/softwareinterfacing and communication between processor andFPGA is established via the PCI bus by shared memoryDMA transfers.This paper presents the methodology and illustratesthe method with an example of a channel coder.