Design and Implementation of a Lossless Parallel High-Speed Data Compression System
IEEE Transactions on Parallel and Distributed Systems
Energy-aware lossless data compression
ACM Transactions on Computer Systems (TOCS)
| Hi-index | 0.00 |
Summary form only presented; substantially as follows. Presents a new compact, power-efficient, and scalable VLSI array for the first Lempel-Ziv (LZ) algorithm to be used in high-speed wireless data communication systems. Lossless data compression can be used to inexpensively halve the amount of data to be transmitted, thus improving the effective bandwidth of the communication channel and in turn, the overall network performance. For wireless networks, the data rate and latency requirement are appropriate for a dedicated VLSI implementation of LZ compression. The nature of wireless networks requires that any additional VLSI hardware also be small, low-power and inexpensive. The architecture uses a novel custom systolic array and a simple dictionary FIFO which is implemented using conventional SRAM. The architecture consists of M simple processing elements where M is the maximum length of the string to be replaced with a codeword, which for practical LAN applications, can range from 16 to 32. The systolic cell has been optimized to remove any superfluous state information or logic, thus making it completely dedicated to the task of LZ compression. A prototype chip has been implemented using 2 /spl mu/s CMOS technology. Using M=32, and assuming a 2:1 compression ratio, the system can process approximately 90 Mbps with a 100 MHz clock rate.