MIES: a microarchitecture design tool

Authors:
J. A. Nestor;B. Soudan;Z. Mayet
Affiliations:
Department of Electrical and Computer Engineering, Illinois Institute of Technology, Chicago, Illinois;Department of Electrical and Computer Engineering, Illinois Institute of Technology, Chicago, Illinois;Department of Electrical and Computer Engineering, Illinois Institute of Technology, Chicago, Illinois
Venue:
MICRO 22 Proceedings of the 22nd annual workshop on Microprogramming and microarchitecture
Year:
1989

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Abstract

This paper describes MIES, a design tool for the modeling, visualization, and analysis of VLSI microarchitectures. MIES combines a graphical data path model and symbolic control model and provides a number of user interfaces which allow these models to be created, simulated, and evaluated.