Using an architectural knowledge base to generate code for parallel computers

• Authors: A. E. Terrano;S. M. Dunn;J. E. Peters
• Venue: CSC '89 Proceedings of the 17th conference on ACM Annual Computer Science Conference
• Year: 1989

Code generation for existing parallel computers involves partitioning the work into schedulable units, assigning the resulting computational units to specific processors, and generating the code for interprocessor communication and synchronization. The options for partitioning and mapping depend in detail on the problem being solved and the algorithm and architecture being used. For each new combination of problem, algorithm, and architecture, a new partitioning and mapping must be created and evaluated based on the actual communication costs incurred. If a particular choice of partition and map is found to be too inefficient when the communication cost is analyzed, it is usually necessary to repeat the code generation process from the beginning.Given the complexity of this problem, it is not practical to develop a general algorithmic approach. A more promising approach is to develop restricted code generation strategies which are suitable for a class of problems and architectures, and compilers which use heuristic advice to guide code generation.In this paper we present a compiler for distributed memory parallel computers which perform automatic program partitioning, mapping and communication code generation under the guidance of a strategy rule-base. All partitioning and mapping is performed automatically, and communication primitives are generated. We describe the compiler system and present an example code generation strategy for iterative elliptic partial differential equation solvers.