LART: Flexible, Low-Power Building Blocks for Wearable Computers

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Venue:
ICDCSW '01 Proceedings of the 21st International Conference on Distributed Computing Systems
Year:
2001

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Application-directed voltage scaling

IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power

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Abstract

Abstract: To ease the implementation of different wearable computers, we developed a low-power processor board (named LART) with a rich set of interfaces. The LART supports dynamic voltage scaling, so performance (and power consumption) can be scaled to match demands: 59-221 MHz, 106-640 mW. High-end wearables can be configured from multiple LARTs operating in parallel; alternatively, FPGA boards can be used for dedicated data-processing, which reduces power consumption significantly.