Synthesis of cyclic encoder and decoder for high speed networks
ISCGAV'05 Proceedings of the 5th WSEAS International Conference on Signal Processing, Computational Geometry & Artificial Vision
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Abstract: The motivation for this paper is the need for high levels of reability in modern telecommunication systems requiring very high data transmission rates. The search for technologicaly independent solutions, easy to implement on low cost and popular devices such as FPGA is an important issue. In this paper, we present a method to improve effectively the speed performance of the polynomial division performed in most error detecting and error correcting circuits. It is based on a pipeline structure for the polynomial division. Furthermore, the proposed solution is fully configurable, both from the static and the dynamic points of view. At synthesis stage, the parallelism level (size of the pipeline structure) and the maximal size of the polynomial divisor must both be chosen. Afterwards, the actual divisor can be chosen and changed while the circuit is running. The architecture proved to be very effective, as data rates up to 2.5 Gbits/s have been reached.