Synthesis of cyclic encoder and decoder for high speed networks

Authors:
Maria Rizzi;Michele Maurantonio;Beniamino Castagnolo
Affiliations:
Dipartimento di Elettrotecnica ed Elettronica, Politecnico di Bari, Bari, Italy;Dipartimento di Elettrotecnica ed Elettronica, Politecnico di Bari, Bari, Italy;Dipartimento di Elettrotecnica ed Elettronica, Politecnico di Bari, Bari, Italy
Venue:
ISCGAV'05 Proceedings of the 5th WSEAS International Conference on Signal Processing, Computational Geometry & Artificial Vision
Year:
2005

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Abstract

In this paper a parallel implementation of an encoder and of a decoder for cyclic codes to increase the bit rate is proposed. The structures are composed of a cascade of iterative combinational cells able to obtain a finite output sequence spatially. The proposed solution allows high bit rates and high degree of modularity, so an easy integration of the circuits is possible. These characteristics make the method suitable to be adopted in a photonic environment in which clocked digital memory elements are still a critical aspect.