Shared memory aware MPSoC software deployment
Proceedings of the Conference on Design, Automation and Test in Europe
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We present a latency-constrained scheduling algorithm to optimize a design for dynamic power. Usage of forces to model power is motivated by the force-directed scheduling (FDS) heuristic proposed by Paulin and Knight [1]. Given a data flow graph (DFG) and an input data environment, we profile the DFG with representative data streams. Our algorithm reduces dynamic power by reducing switched capacitance inside resources. The switched capacitance of combinations among DFG operations, which could share a resource, and the probability of selecting such a combination, are evaluated. Switched capacitance inside a module is modeled as the spring constant k and probability of selecting the corresponding combination is modeled as the displacement x, in the force equation F = kx. Thus, a force is associated with each feasible combination corresponding to its power cost. Due to numerous possibilities, we obtain a distribution of forces whose mean, standard deviation, and skew are used to make a power-optimal scheduling decision. Compared to original FDS, our algorithm shows average power savings of 16.4% for the same throughput at the cost of a nominal area overhead.