The turn model for adaptive routing
ISCA '92 Proceedings of the 19th annual international symposium on Computer architecture
Force-Directed Scheduling for Dynamic Power Optimization
ISVLSI '02 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
Bandwidth-Constrained Mapping of Cores onto NoC Architectures
Proceedings of the conference on Design, automation and test in Europe - Volume 2
SUNMAP: a tool for automatic topology selection and generation for NoCs
Proceedings of the 41st annual Design Automation Conference
Exploiting the Routing Flexibility for Energy/Performance Aware Mapping of Regular NoC Architectures
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
NoC Synthesis Flow for Customized Domain Specific Multiprocessor Systems-on-Chip
IEEE Transactions on Parallel and Distributed Systems
Mapping and physical planning of networks-on-chip architectures with quality-of-service guarantees
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
A Force-directed Approach for Fast Generation of Efficient Multi-Port NoC Architectures
VLSID '07 Proceedings of the 20th International Conference on VLSI Design held jointly with 6th International Conference: Embedded Systems
Control-Flow Aware Communication and Conflict Analysis of Parallel Processes
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Application mapping for chip multiprocessors
Proceedings of the 45th annual Design Automation Conference
Energy-Aware Task Allocation for Network-on-Chip Based Heterogeneous Multiprocessor Systems
PDP '11 Proceedings of the 2011 19th International Euromicro Conference on Parallel, Distributed and Network-Based Processing
Memory Access Aware Mapping for Networks-on-Chip
RTCSA '11 Proceedings of the 2011 IEEE17th International Conference on Embedded and Real-Time Computing Systems and Applications - Volume 01
Distance-Constrained Force-Directed Process Mapping for MPSoC Architectures
DSD '12 Proceedings of the 2012 15th Euromicro Conference on Digital System Design
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In this paper we present a novel approach for mapping interconnected software components onto cores of homogenous MPSoC architectures. The analytic mapping process considers shared memory communication as well as the routing algorithm controlling packet-based communication. The software components are mapped with the constraints of avoiding communication conflicts as well as access conflicts to shared memory resources. The core of the elaborated approach consists of an algorithm for software mapping which is inspired by force-directed scheduling from high-level synthesis. Experimental results show that the presented approach increases the overall system performance by 22% while reducing the average communication latency by 35%. For presenting the major advantages of the developed solution, we optimized an advanced driver assistance system on the Tilera TILEPro64 processor.