Energy-Aware Task Allocation for Network-on-Chip Based Heterogeneous Multiprocessor Systems

Authors:
Jia Huang;Christian Buckl;Andreas Raabe;Alois Knoll
Affiliations:
-;-;-;-
Venue:
PDP '11 Proceedings of the 2011 19th International Euromicro Conference on Parallel, Distributed and Network-Based Processing
Year:
2011

Citing 0
Cited 3

A survey on application mapping strategies for Network-on-Chip design

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Shared memory aware MPSoC software deployment

Proceedings of the Conference on Design, Automation and Test in Europe
From UML specifications to mapping and scheduling of tasks into a NoC, with reliability considerations

Journal of Systems Architecture: the EUROMICRO Journal

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Abstract

Energy-efficiency is becoming one of the most critical issues in embedded system design. In Network-on-Chip (NoC) based heterogeneous Multiprocessor Systems, the energy consumption is influenced dramatically by task allocation schemes. Although various approaches are proposed to allocate tasks in an energy-efficient way, existing work does not well explore the tradeoff between the two major power consumers, namely the processors and network links, resulting in sub optimal mappings from a system point of view. In this paper, we first extend the existing Integer Linear Programming (ILP) formulation to take both processing and communication energy into account. Thereafter, we propose a Simulated Annealing with Timing Adjustment (SA-TA) heuristic to accelerate the optimization process. While the SA-TA algorithm achieves performance very close to the global optimum, significant improvement in computation speed is observed.