A Force-directed Approach for Fast Generation of Efficient Multi-Port NoC Architectures

Authors:
Balasubramanian Sethuraman;Ranga Vemuri
Affiliations:
University of Cincinnati, Cincinnati, OH;University of Cincinnati, Cincinnati, OH
Venue:
VLSID '07 Proceedings of the 20th International Conference on VLSI Design held jointly with 6th International Conference: Embedded Systems
Year:
2007

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Abstract

Networks-on-Chip (NoC) is an emerging style of system design introduced to overcome the communi- cation and the performance bottlenecks of a shared- bus design. Away from the traditional NoC mesh de- sign, Multi Local Port Router (MLPR) has been intro- duced as design alternative to improve the bandwidth, reduce the network area (36% average area savings) and eventually, improve the overall performance of the NoC system. In this research, we present a fast map- ping tool (cMap) for generating NoC architectures us- ing MLPRs. The algorithm exploits the advantages of- fered by MLPRs and starts with a minimum dimen- sion mesh. After an initial bandwidth-communication- cost based nearest-neighbor placement, it uses a force- directed approach to iteratively expand the mesh, as the cost gets reduced. The algorithm introduces the concept of Folding to improve the NoC design. Unlike the ear- lier exhaustive-search based optiMap algorithm, cMap can handle any size of the task graph, producing near- optimal results (average cost difference between 3% and 10%) in a couple of seconds. We experiment with a rich set of 22 benchmarks and report the results.