Error Correcting Strategy for High Speed and High Density Reliable Flash Memories
Journal of Electronic Testing: Theory and Applications
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Abstract: This paper presents a new scheme for error control coding in multilevel Flash memories. The n bits stored in a single memory cell are organized in different "bit-layers", which are independent from one another. Error correction is carried out separately for each bit-layer. The correction of any failure in a single memory cell is therefore achieved by using a simple error control code (ECC) providing single-bit correction, regardless of the number of bits stored in a single cell. This greatly simplifies the encoding and decoding circuits and minimizes the impact of ECC time overhead on memory access time. Moreover the same encoding/decoding circuit and check cells are used with multilevel memories working at a variable number of bits per cell.