Partial scan designs without using a separate scan clock

• Authors: Kwang-Ting Cheng
• Venue: VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
• Year: 1995

Abstract: Existing flip-flop selection and test generation methods for partial scan designs assume the use of a separate scan clock. With a separate clock for the scan operation, the states of the non-scan flip-flops can be frozen during the scan operation and any state can be scanned into the scan register without affecting the states of the non-scan flip-flops. Under this assumption, test vectors can be efficiently generated by a sequential circuit test generator. However, this requirement results in the need for multiple clock trees and poses problems in the routing of clock signals that, in general, are subject to a tight constraint on clock skew. In this paper, we lift this assumption and address the problems of test generation, scan flip-flop selection and ordering of scan registers for partial scan designs that use the system clock for the scan operation. An existing test generation algorithm is modified to incorporate the scan-shifting concept for such designs. This modified test generation scheme also implicitly compacts the test vectors and results in significantly reduction in the length of test vectors as shown by our experimental results on ISCAS89 benchmark circuits. The test vectors generated by this method can be applied at speed and thus can also detect delay faults. We show that cycle breaking remains to be an effective heuristic for scan flip-flop selection for our test generation method. The ordering of scan flip-flops in the scan chain affects the final fault coverage for the new test generation method. We formulate the ordering problem as a combinatorial optimization problem. Experimental results on test generation and ordering of scan flip-flops are presented to show the effectiveness of our approach.