Efficient RT-level fault diagnosis methodology
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Efficient RT-level fault diagnosis
Journal of Computer Science and Technology
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The rapid rise in size and complexity of VLSI circuits has stimulated a need to handle fault simulation at higher levels of abstraction. We outline an RT-level fault simulation technique that utilizes symbolic data to group fault effects. Experimental results show that the proposed methodology provides superior speed-ups and accurate fault coverages.