Refining a high level systemC model

Authors:
Bernhard Niemann;Frank Mayer;Francisco Javier;Rabano Rubio;Martin Speitel
Affiliations:
Fraunhofer Institute for Integrated Circuits, Erlangen, Germany;Fraunhofer Institute for Integrated Circuits, Erlangen, Germany;Fraunhofer Institute for Integrated Circuits, Erlangen, Germany;Fraunhofer Institute for Integrated Circuits, Erlangen, Germany;Fraunhofer Institute for Integrated Circuits, Erlangen, Germany
Venue:
SystemC
Year:
2003

Citing 0
Cited 3

Towards a heterogeneous simulation kernel for system level models: a SystemC kernel for synchronous data flow models

Proceedings of the 14th ACM Great Lakes symposium on VLSI
Truly heterogeneous modeling with systemC

Formal methods and models for system design
A SystemC-based design methodology for digital signal processing systems

EURASIP Journal on Embedded Systems

Quantified Score

Hi-index	0.00

Visualization

Abstract

The objective of this paper is to present a possible flow, using SystemC, to make the transition from a high level data flow description towards an implementable model. The main focus is behavior refinement, in other words the modification of the module descriptions until they can be mapped to a given architecture, satisfying the implementation constraints. A customizable processor core that executes an ANSI C version of the system model is utilized. Only operations that require a lot of computational power are implemented as custom hardware modules to extend the core functionality. A simple operator counting technique is used inside the high level model to obtain run time estimates for hardware-software partitioning.