Iterative compaction: an improved approach to graph and circuit bisection
EURO-DAC '91 Proceedings of the conference on European design automation
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This paper introduces a new divide-and-conquer framework for VLSI graph layout. Universally close upper and lower bounds are obtained for important cost functions such as layout area and propagation delay. The framework is also effectively used to design regular and configurable layouts, to assemble large networks of processor using restructurable chips, and to configure networks around faulty processors. It is also shown how good graph partitioning heuristics may be used to develop provably good layout strategy.