Iterative compaction: an improved approach to graph and circuit bisection

Authors:
J. Haralambides;F. Makedon
Affiliations:
The University of Texas at Dallas, Richardson, TX;The University of Texas at Dallas, Richardson, TX
Venue:
EURO-DAC '91 Proceedings of the conference on European design automation
Year:
1991

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Abstract

Given a graph G= (V, E), graph bisection is the problem of finding a partition of the vertex set V into two equal-sized subsets V1 and V2 so that the number of edges between them is minimized. This problem has important applications in circuit partitioning, testing, VLSI design and other network-related problems that apply the divide-and-conquer strategy. We introduce a new heuristic approach, called Iterative Compaction (IC), which employees a node degree based matching and iterative graph compaction. This gives a significant improvement over the performance of known bisection algorithms in both time and quality of the results.