SPUR: A VLSI Multiprocessor Workstation

Authors:
Mark D Hill;Susan J. Eggers;James R Larus;George S. Taylor;Glenn D. Adams;Bidyut K Bose;Garth A. Gibson;Paul M Hansen;John Keller;Shing I. Kong;Corinna G Lee;Daebum Lee;J. M. Pendleton;Scott A Ritchie;David A. Wood;Benjamin G. Zorn;Paul N. Hilfinger;D. A. Hodges;Randy H. Katz;John K. Ousterhout;David A. Patterson
Affiliations:
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Venue:
SPUR: A VLSI Multiprocessor Workstation
Year:
1985

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Abstract

SPUR (Symbolic Processing Using RISCs) is a workstation for conducting parallel processing research. SPUR contains 6 to 12 high-performance homogeneous processors connected with a shared bus. The number of processors is large enough to permit parallel processing experiments, but small enough to allow packaging as a personal workstation. The restricted processor count also allows us to build powerful RISC processors, which include support for Lisp and IEEE floating-point, at reasonable cost. This paper presents a specification of SPUR and the results of some early architectural experiments. SPUR features include a large virtually-tagged cache, address translation without a translation buffer, LISP support with datatype tags but without microcode, multiple cache consistency in hardware, and an IEEE floating-point coprocessor without microcode.