On accelerating the neighbours lists generation process using field programmable gate arrays
ISPRA'05 Proceedings of the 4th WSEAS International Conference on Signal Processing, Robotics and Automation
Traversal caches: a first step towards FPGA acceleration of pointer-based data structures
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
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FPGAs have appealing features such as customizable internaland external bandwidth and the ability to exploit vastamounts of fine-grain parallelism. In this paper we explorethe applicability of these features in using FPGAs as smartmemory engines for search and reorganization computationsover spatial pointer-based data structures. The experimentalresults in this paper suggests that reconfigurable logic, whencombined with data reorganization, can lead to dramaticperformance improvements of up to 20x over traditionalcomputer architectures for pointer-based computations,traditionally not viewed as a good match for reconfigurabletechnologies.