Application-specific instruction set processor implementation of list sphere detector
EURASIP Journal on Embedded Systems
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A common approach to enhance the performance of processorsis to increase the number of function units whichoperate concurrently. We observe this development in allrecent superscalar and VLIW (very long instruction word)processors. VLIWs are easier extensible to high performanceranges because they lack much of the superscalarhardware required for dependence checking and hardwareresource allocation; instead they rely on a compiler to performthese tasks.In this paper we propose to proceed along this line andgo one step further in replacing hardware by software complexity:a new architecture is proposed which requires thescheduling and allocation of transports at compile-time, insteadof performing this at run-time. This reduces hardwarecomplexity and creates several new compile-time optimizations.The paper illustrates the compilation steps required,explains the concept and characteristics of the proposedarchitecture, and shows several measurements whichconfirm our belief that, especially for high performanceembedded applications, this architecture is very attractive.