Understanding Video Pixel Processing Applications for Flexible Implementations

  • Authors:
  • Om Prakash Gangwal;Johan Janssen;Selliah Rathnam;Erwin Bellers;Marc Duranton

  • Affiliations:
  • -;-;-;-;-

  • Venue:
  • DSD '03 Proceedings of the Euromicro Symposium on Digital Systems Design
  • Year:
  • 2003

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Abstract

Media processing system-on-chips (SoCs) mainly consist of audioencoding/decoding (e.g. AC-3, MP3), video encoding/decoding(e.g. H263, MPEG-2) and video pixel processing functions (e.g.de-interlacing, noise reduction). Video pixel processing functionshave very high computational demands, as they require a largeamount of computations on large amount of data (note that thedata are pixels of completely decoded pictures). In this paper, wefocus on video pixel processing functions. Usually, thesefunctions are implemented in dedicated hardware. However,flexibility (by means of programmability or reconfigurability) isneeded to introduce the latest innovative algorithms, to allowdifferentiation of products, and to allow bug fixing afterfabricating chips. It is impossible to fulfill the computationalrequirements of these functions by current programmable mediaprocessors.To achieve efficient implementations for flexible solutions, wewill study, in this paper, the application characteristics of somerepresentative video pixel processing functions. Thecharacteristics considered are granularity of operations, amountand kind of data accesses and degree of parallelism present inthese functions. We observe that from computational granularitypoint of view many functions can be expressed in terms of kernelse.g. Median3 (i.e. median of three values), finite impulse response(FIR) filters, table lookups (LUT) etc. that are coarser grain thanALU, Mult, MAC, etc. Regarding the kind of data accesses, wecategorize these functions as regular, regular with some datarearrangement and irregular data access patterns. Furthermore, thedegree of parallelism present in these functions is expressed interms of data level parallelism (DLP) and instruction/operationlevel parallelism (ILP). We show with an example that theseproperties can be exploited to make specialized programmableprocessors.