A multithreading embedded architecture
DNCOCO'08 Proceedings of the 7th conference on Data networks, communications, computers
Proceedings of the 14th ACM SIGPLAN/SIGBED conference on Languages, compilers and tools for embedded systems
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In this paper we present a framework for dynamic application customizationfor high-performance and low-power embedded processors.The proposed architecture is capable of utilizing applicationinformation to boost the performance and lower the power consumptionof the most important microarchitectural components such asinstruction/data caches and the memory subsystem. We present adesign framework, including CAD support infrastructure and reprogrammablehardware support, for a dynamically customizable microarchitecture.We outline the underlying algorithms for compile-timeextraction of the utilized application properties and we presentthe architectural principles of the hardware support. Extensive experimentalresults confirm the efficacy of this novel embedded processorarchitecture.