A Methodology for CMOS Low Noise Ampli.er Design

Authors:
Elkim Roa;João Navarro Soares;Wilhelmus Van Noije
Affiliations:
-;-;-
Venue:
SBCCI '03 Proceedings of the 16th symposium on Integrated circuits and systems design
Year:
2003

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Abstract

An intuitive strategy for CMOS low noise amplifier (LNA) design, compromising noise and linearity performance optimization, is presented. Analytical expressions for noise factor and IM3 are derived. The gain and power dissipation are considered pre-fixed parameters for this approach. A 2.4 GHz LNA has been designed and simulated in a 0.35 µm CMOS technology to validate the proposed methodology.