A Methodology for CMOS Low Noise Ampli.er Design
SBCCI '03 Proceedings of the 16th symposium on Integrated circuits and systems design
Convex Optimization
An improved and automated design tool for the optimization of CMOS OTAs using geometric programming
Proceedings of the 21st annual symposium on Integrated circuits and system design
Robust Analog/RF Circuit Design With Projection-Based Performance Modeling
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper presents the design using geometric programming of a merged CMOS LNA-Mixer cell, intended for bluetooth application at 2.45GHz. A rigorous noise formulation taking into account on chip inductors non-idealities and parameters from inductor measurement results is provided. Design considerations to achieve geometric programming suitable expressions for noise, gain, and input matching, among others, are presented. As a result, the designed LNA-Mixer cell exhibits a single side band noise figure of 9.64dB, with a voltage gain of 21.5dB, input reflection co-efficient S11 of -28.7dB, in addition to a PIIP3=-2.06dBm. The circuit area is 0.93mm2 and consumes 8.67mW at 3.3V power supply in a 0.35μm CMOS process.