VLSI: placement based on routing and timing information

Authors:
J. Garbers;B. Korte;H. J. Prömel;E. Schwietzke;A. Steger
Affiliations:
Forschungsinstitut für Diskrete Mathematik, Bonn, West Germany;Forschungsinstitut für Diskrete Mathematik, Bonn, West Germany;Forschungsinstitut für Diskrete Mathematik, Bonn, West Germany;Forschungsinstitut für Diskrete Mathematik, Bonn, West Germany;Forschungsinstitut für Diskrete Mathematik, Bonn, West Germany
Venue:
EURO-DAC '90 Proceedings of the conference on European design automation
Year:
1990

Citing 3
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Abstract

In this paper we propose a hierarchical placement procedure incorporating more and more detailed routing and timing information at increasing levels of the hierarchy. This procedure is based on the well-known min-cut method. A global routing and a timing analysis are computed after every cut and are used to guide the subsequent cell partitioning.