A linear-time heuristic for improving network partitions
DAC '82 Proceedings of the 19th Design Automation Conference
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A novel approach for gate-matrix synthesis starting from an EDIF logical network description is presented. The networks are automatically decomposed into gate-matrix 'macrocells' with approximately equal layout area using a very effective algorithm, which is adapted to the layout topology, featuring simultaneous module placement in conjunction with a new reliable module area estimation technique.Dramatic improvements in overall layout generation time and layout area are achieved; area savings are significantly higher than previously reported.