The use of inverse layout trees for hierarchical design rule checking
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Comparing structurally different views of a VLSI design
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Introduction to VLSI Systems
The Design and Analysis of Computer Algorithms
The Design and Analysis of Computer Algorithms
The quad-CIF tree: A data structure for hierarchical on-line algorithms
DAC '82 Proceedings of the 19th Design Automation Conference
Optimal height reduction problems for tree-structured hierarchies
Nordic Journal of Computing
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VLSI mask layouts usually have a hierarchical representation which serves to record the structure of the design while saving storage space. It is often convenient to work directly on such a representation for performing some operations. However for many other operations it is preferable to work on the flattened representation of the circuit. In this paper we look at the unnesting operation on layouts to demonstrate that simple transformations of one hierarchy to an equivalent one help tremendously in improving the performance of typical operations on hierarchical layout representations, while not requiring as much memory as flattened representations.