A linear-time heuristic for improving network partitions
DAC '82 Proceedings of the 19th Design Automation Conference
A timing driven N-way chip and multi-chip partitioner
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
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This paper discusses the generalization of the Fiduccia-Mattheyses linear time bi-partitioning algorithm to a linear time n-partitioning algorithm. It uses a new heuristic cost function to evaluate the cost of arbitrarily large spanning trees in O(log n) time. Practical experiments show good results.