Improved placement for hierarchical FPGAs exploiting local interconnect resources
Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes
Integration of Net-Length Factor with Timing- and Routability-Driven Clustering Algorithms
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
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With increasing device and design sizes, InterconnectPlanning is fast becoming an important design issue for largeFPGA based designs. The fundamental requirement for interconnectplanning is the ability to estimate the routing requirementsof a given design at all stages of physical design. A numberof interconnect estimation methods have been proposed, butvery few operate prior to placement. Pre-placement estimationis very useful for detailed design space exploration during logicsynthesis and earlier stages of design. We propose a new localneighborhood analysis based method to estimate the wirelengthsof every net in a given netlist, prior to placement. We assume anoptimal placement with respect to total wirelength and estimatethe bounding-box sizes of all the nets. We then use the bounding-boxestimates to compute the post-routing peak channel widthof the device. Our method efficiently handles pad constraineddesigns. We compare our net bounding-box and peak channelwidth estimates with the post-placement and post-routing resultsobtained using VPR [1], a commonly used FPGA tool suite.